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Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis of HDL designs, superseding Xilinx ISE with additional features for system on a chip development and high-level synthesis.〔(【引用サイトリンク】title=Xilinx and its Ecosystem Demonstrate All Programmable and Smarter Vision Solutions at ISE 2015 )〕 Vivado represents a ground-up rewrite and re-thinking of the entire design flow (compared to ISE), and has been described by reviewers as "well conceived, tightly integrated, blazing fast, scalable, maintainable, and intuitive".〔(Vivado Design Suite ), Xilinx Website〕〔(Vivado Design Suite ), First version released in 2012, Xilinx Downloads〕 Unlike ISE which relied on ModelSim for simulation,〔(Circuit Design with VHDL ), MIT Press, 2004〕〔(Advances in Computer Science and Information Engineering ), Springer Science & Business Media, 11-May-2012〕 the Vivado System Edition includes an in-built logic simulator.〔(Vivado Features ), Xilinx〕 Vivado also introduces high-level synthesis, with a toolchain that converts C code into programmable logic.〔 Vivado has been described as a "state-of-the-art comprehensive EDA tool with all the latest bells and whistles in terms of data model, integration, algorithms, and performance". In 2013, Xilinx completed a 1000 person-year (US$200 million) development of its Vivado Design Suite, replacing the 15-year old ISE. ==Features== Vivado enables developers to synthesize (compile) their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Vivado is a design environment for FPGA products from Xilinx, and is tightly-coupled to the architecture of such chips, and cannot be used with FPGA products from other vendors. Vivado was introduced in April 2012, and is an integrated design environment (IDE) with a system-to-IC level tools built on a shared scalable data model and a common debug environment. Vivado includes electronic system level (ESL) design tools for synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems.〔EDN. "(The Vivado Design Suite accelerates programmable systems integration and implementation by up to 4X )." Jun 15, 2012. Retrieved Jun 25, 2013.〕 A free version WebPACK Edition of Vivado provides designers with a limited version of the design environment.〔Clive Maxfield, EE Times. "(WebPACK edition of Xilinx Vivado Design Suite now available )." Dec 20, 2012. Retrieved Jun 25, 2013.〕 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Xilinx Vivado」の詳細全文を読む スポンサード リンク
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